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ST SPC560P34 - Table 295. MCR Field Descriptions

ST SPC560P34
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RM0046 Analog-to-Digital Converter (ADC)
Doc ID 16912 Rev 5 589/936
Table 295. MCR field descriptions
Field Description
OWREN
Overwrite enable
This bit enables or disables the functionality to overwrite unread converted data.
0 Prevents overwrite of unread converted data; new result is discarded
1 Enables converted data to be overwritten by a new conversion
WLSIDE
Write left/right-aligned
0 The conversion data is written right-aligned.
1 Data is left-aligned (from 15 to (15 resolution + 1)).
The WLSIDE bit affects all the CDR registers simultaneously. See Figure 300 and Figure 300.
MODE
One Shot/Scan
0 One Shot Mode—Configures the normal conversion of one chain.
1 Scan Mode—Configures continuous chain conversion mode; when the programmed chain
conversion is finished it restarts immediately.
NSTART
Normal Start conversion
Setting this bit starts the chain or scan conversion. Resetting this bit during scan mode causes
the current chain conversion to finish, then stops the operation.
This bit stays high while the conversion is ongoing (or pending during injection mode).
0 Causes the current chain conversion to finish and stops the operation
1 Starts the chain or scan conversion
JTRGEN
Injection external trigger enable
0 External trigger disabled for channel injection
1 External trigger enabled for channel injection
JEDGE
Injection trigger edge selection
Edge selection for external trigger, if JTRGEN = 1.
0 Selects falling edge for the external trigger
1 Selects rising edge for the external trigger
JSTART
Injection start
Setting this bit will start the configured injected analog channels to be converted by software.
Resetting this bit has no effect, as the injected chain conversion cannot be interrupted.
CTUEN
Cross trigger unit conversion enable
0 CTU triggered conversion disabled
1 CTU triggered conversion enabled
ADCLKSEL
Analog clock select
This bit can only be written when ADC in Power-Down mode
0 ADC clock frequency is half Peripheral Set Clock frequency
1 ADC clock frequency is equal to Peripheral Set Clock frequency
ABORTCHAIN
Abort Chain
When this bit is set, the ongoing Chain Conversion is aborted. This bit is reset by hardware as
soon as a new conversion is requested.
0 Conversion is not affected
1 Aborts the ongoing chain conversion

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