ST SPC560P34 - Functional Description

Clock Description RM0046
110/936 Doc ID 16912 Rev 5
4.9.3 Functional description
The clock and frequency names referenced in this block are defined as follows:
● CK_XOSC: clock coming from the external crystal oscillator
● CK_IRC: clock coming from the low frequency internal RC oscillator
● CK_PLL: clock coming from the PLL
● f
XOSC
: frequency of external crystal oscillator clock
● f
RC
: frequency of low frequency internal RC oscillator
● f
PLL
: frequency of FMPLL clock
Crystal clock monitor
If f
XOSC
is smaller than f
RC
divided by 2
RCDIV
bits of CMU_0_CSR and the CK_XOSC is ‘ON’
and stable as signaled by the ME, then:
● An event pending bit OLRI in CMU_0_ISR is set
● A failure event OLR is signaled to the RGM and FCU, which in turn can generate either
an interrupt, a reset, or a SAFE mode request.
PLL clock monitor
The PLL clock CK_PLL frequency can be monitored by programming bit CME_0 of the
CMU_0_CSR to ‘1’. The CK_PLL monitor starts as soon as bit CME_0 is set. This monitor
can be disabled at any time by writing bit CME_0 to ‘0’.
If the CK_PLL frequency (f
PLL
) is greater than a reference value determined by bits
HFREF[11:0] of the CMU_HFREFR and the CK_PLL is ‘ON’ and the PLL locked as signaled
by the ME then:
● An event pending bit FHHI_0 in the CMU_0_ISR is set.
● A failure event FHH is signaled to the RGM and FCU, which in turn can generate either
an interrupt, a reset, or a SAFE mode request.
If f
PLL
is less than a reference clock frequency (f
RC
/4) and the CK_PLL is ‘ON’ and the PLL
locked as signaled by the ME, then:
● An event pending bit FLCI_0 in the CMU_0_ISR is set.
● A failure event FLC is signaled to the RGM and FCU, which in turn can generate either
an interrupt, a reset, or a SAFE mode request.
If f
PLL
is less than a reference value determined by bits LFREF[11:0] of the CMU_LFREFR
and the CK_PLL is ‘ON’ and the PLL locked as signaled by the ME, then:
● An event pending bit FLLI_0 in the CMU_0_ISR is set.
● A failure event FLL is signaled to the RGM and FCU, which in turn can generate either
an interrupt, a reset, or a SAFE mode request.
Note: It is possible for either the XOSC or PLL monitors to produce a false event when the XOSC
or PLL frequency is too close to RC/2
RCDIV
frequency due to an accuracy limitation of the
compare circuitry.
System clock monitor
The system clock is monitored by CMU_1. The F
SYS_CLK
frequency can be monitored by
programming CMU_1_CSR[CME] = 1. SYS_CLK monitoring starts as soon as
CMU_1_CSR[CME] = 1. This monitor can be disabled at any time by writing CME bit to 0.