RM0046 Error Correction Status Module (ECSM)
Doc ID 16912 Rev 5 295/936
where the combination of a properly enabled category in the ECR and the detection of the
corresponding condition in the ESR produces the interrupt request.
The ECSM allows a maximum of one bit of the ESR to be asserted at any given time. This
preserves the association between the ESR and the corresponding address and attribute
registers, which are loaded on each occurrence of an properly enabled ECC event. If there
is a pending ECC interrupt and another properly enabled ECC event occurs, the ECSM
hardware automatically handles the ESR reporting, clearing the previous data and loading
the new state and thus guaranteeing that only a single flag is asserted.
To maintain the coherent software view of the reported event, the following sequence in the
ECSM error interrupt service routine is suggested:
1. Read the ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ESR and verify the current contents matches the original contents. If the
two values are different, go back to step 1 and repeat.
4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt
request.
Figure 132. ECC Status register (ESR)
Address:
Base + 0x0047 Access: User read/write
01234567
R0 0
R1BC F1BC
00
RNCE FNCE
W
Reset00000000
Table 122. ESR field descriptions
Field Description
2
R1BC
RAM 1-bit Correction
This bit can only be set if ECR[ER1BR] is asserted. The occurrence of a properly enabled single-bit
RAM correction generates a ECSM ECC interrupt request. The address, attributes and data are also
captured in the REAR, RESR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1
to this bit. Writing a 0 has no effect.
0 No reportable single-bit RAM correction detected
1 Reportable single-bit RAM correction detected
3
F1BC
Flash 1-bit Correction
This bit can only be set if ECR[EF1BR] is asserted. The occurrence of a properly enabled single-bit
flash correction generates a ECSM ECC interrupt request. The address, attributes and data are also
captured in the FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this
bit. Writing a 0 has no effect.
0 No reportable single-bit flash correction detected
1 Reportable single-bit flash correction detected
To Next Page
Loading...
Need help?
General
