FlexCAN RM0046
566/936 Doc ID 16912 Rev 5
Message Buffer lock mechanism
Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive
process. When the CPU reads the Control and Status word of an “active not empty” Rx MB,
FlexCAN assumes that the CPU wants to read the whole MB in an atomic operation, and
thus it sets an internal lock flag for that MB. The lock is released when the CPU reads the
Free Running Timer (global unlock operation), or when it reads the Control and Status word
of another MB. The MB locking is done to prevent a new frame to be written into the MB
while the CPU is reading it.
Note: The locking mechanism only applies to Rx MBs that have a code different than INACTIVE
(‘0000’) or EMPTY
(b)
(‘0100’). Also, Tx MBs can not be locked.
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the
array are programmed with the same ID, and FlexCAN has already received and stored
messages into these two MBs. Suppose now that the CPU decides to read MB number 5
and at the same time another message with the same ID is arriving. When the CPU reads
the Control and Status word of MB number 5, this MB is locked. The new message arrives
and the matching algorithm finds out that there are no “free to receive” MBs, so it decides to
override MB number 5. However, this MB is locked, so the new message can not be written
there. It will remain in the SMB waiting for the MB to be unlocked, and only then will be
written to the MB. If the MB is not unlocked in time and yet another new message with the
same ID arrives, then the new message overwrites the one on the SMB and there will be no
indication of lost messages either in the Code field of the MB or in the Error and Status
Register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code
field is asserted. If the CPU reads the Control and Status word and finds out that the BUSY
bit is set, it should defer accessing the MB until the BUSY bit is negated.
Note: If the BUSY bit is asserted or if the MB is empty, then reading the Control and Status word
does not lock the MB.
Deactivation takes precedence over locking. If the CPU deactivates a locked Rx MB, then its
lock status is negated and the MB is marked as invalid for the current matching round. Any
pending message on the SMB will not be transferred anymore to the MB.
22.4.7 Rx FIFO
The receive-only FIFO is enabled by asserting the FEN bit in the MCR. The reset value of
this bit is zero to maintain software backwards compatibility with previous versions of the
module that did not have the FIFO feature. When the FIFO is enabled, the memory region
normally occupied by the first 8 MBs (0x80-0xFF) is now reserved for use of the FIFO
engine (see Section 22.3.3, “Rx FIFO structure). Management of read and write pointers is
done internally by the FIFO engine. The CPU can read the received frames sequentially, in
the order they were received, by repeatedly accessing a Message Buffer structure at the
beginning of the memory.
The FIFO can store as many as six frames pending service by the CPU. An interrupt is sent
to the CPU when new frames are available in the FIFO. Upon receiving the interrupt, the
CPU must read the frame (accessing an MB in the 0x80 address) and then clear the
interrupt. The act of clearing the interrupt triggers the FIFO engine to replace the MB in 0x80
b. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. In current FlexCAN versions,
this behavior is maintained when the BCC bit is negated.
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