ST SPC560P34 - Available Clock Domains; FMPLL Input Reference Clock; Figure 11. SPC560 P40;34 System Clock Distribution Part B

Clock Description RM0046
94/936 Doc ID 16912 Rev 5
Figure 11. SPC560P40/34 system clock distribution Part B
4.2 Available clock domains
This section describes the various clock domains available on SPC560P40/34.
4.2.1 FMPLL input reference clock
The input reference clock for FMPLL_0 is always the external crystal oscillator clock
(XOSC).
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
IRCOSC_CLK
SYS_CLK
IRCOSC_CLK
XOSC_CLK
SYS_CLK
IPS
SYS_CLK
IPS
SYS_CLK
LINFlex_0
Module clock
BIU
LINFlex_1
Module clock
BIU
DMA Mux
Module clock
BIU
eDMA2
Module clock
BIU
INTC
Module clock
BIU
SWT
Module clock
Protocol clock
BIU
FlexCAN
Module clock
Protocol clock
BIU
FCU
Module clock
Protocol clock
BIU
STM
Module clock
BIU
ECSM
Module clock
BIU
SIUL
Module clock
BIU
SSCM
Module clock
BIU
WKPU
Module clock
BIU
PIT/RTI
Module clock
BIU
Data Flash 0
Code Flash 0
MC Unit
Module clock
BIU
ME
CGM
RGM
PCU
PMU
FMPLL_0
CQM_0
IRCOSC
XOSC
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
SYS_CLK
Platform Flash Controller
Module clock
BIU