ST SPC560P34 User Manual

RM0046 System Integration Unit Lite (SIUL)
Doc ID 16912 Rev 5 251/936
11.5 Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module.
11.5.1 SIUL memory map
Table 9 0 lists the SIUL registers.
Table 90. SIUL memory map
Offset from
SIUL_BASE
(0xC3F9_0000)
Register Location
0x0000–0x0003 Reserved
0x0004 MCU ID Register #1 (MIDR1) on page 11-252
0x0008 MCU ID Register #2 (MIDR2) on page 11-254
0x000C–0x0013 Reserved
0x0014 Interrupt Status Flag Register (ISR) on page 11-255
0x0018 Interrupt Request Enable Register (IRER) on page 11-255
0x001C–0x0027 Reserved
0x0028 Interrupt Rising-Edge Event Enable Register (IREER) on page 11-256
0x002C Interrupt Falling-Edge Event Enable Register (IFEER) on page 11-256
0x0030 Interrupt Filter Enable Register (IFER) on page 11-257
0x0034–0x003F Reserved
0x0040–0x00CE Pad Configuration Registers (PCR[0:71]) on page 11-257
0x00D0–0x04FF Reserved
0x0500–0x0520
Pad Selection for Multiplexed Inputs registers
(PSMI[0_3:32_35])
on page 11-259
0x0524–0x05FF Reserved
0x0600–0x0644
GPIO Pad Data Output registers 0_3–68_71
(GPDO[0_3:68_71])
on page 11-262
0x 0648 –0x07FF Reserved
0x0800–0x
0844
GPIO Pad Data Input registers 0_3–68_71
(GPDI[0_3:68_71])
on page 11-262
0x0848–0x0BFF Reserved
0x0C00–0x0C0C Parallel GPIO Pad Data Out register 0–3 (PGPDO[0:3]) on page 11-263
0x0C10–0x0C3F Reserved
0x0C40–0x0C4C Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3]) on page 11-263
0x0C50–0x0C7F Reserved
0x0C80–0x0C98
Masked Parallel GPIO Pad Data Out register 0–6
(MPGPDO[0:6])
on page 11-264
0x0C9C– 0x0FFF Reserved

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English