Nexus Development Interface (NDI) RM0046
880/936 Doc ID 16912 Rev 5
Debug Status Register (DBSR)
The Debug Status Register (DBSR) contains status on debug events and the most recent
processor reset. The Debug Status Register is set via hardware, and read and cleared via
software. Bits in the Debug Status Register can be cleared using mtspr DBSR,RS. Clearing
is done by writing to the Debug Status Register with a 1 in any bit position that is to be
cleared and 0 in all other bit positions. The write data to the Debug Status Register is not
direct data, but a mask. A ‘1’ causes the bit to be cleared, and a ‘0’ has no effect. Debug
Status bits are set by Debug events only while Internal Debug Mode is enabled or External
Debug Mode is enabled. When debug interrupts are enabled (MSR
DE
=1 DBCR0
IDM
=1 and
DBCR0
EDM
=0, or MSR
DE
=1, DBCR0
IDM
=1 and DBCR0
EDM
=1 and software is allocated
resource(s) via DBERC0), a set bit in DBSR owned by software other than MRR or VLES
will cause a debug interrupt to be generated. The debug interrupt handler is responsible for
clearing DBSR bits prior to returning to normal execution. The Power Architecture
technology VLE APU adds the DBSR
VLES
status bit to indicate debug events occurring due
to a Power Architecture technology VLE instruction. When resource sharing is enabled,
(DBCR0
EDM
=1 and DBERC0
IDM
=1), only software-owned resources may be modified by
software, and all status bits associated with hardware-owned resources will be forced to ‘0’
in DBSR when read by software via a mfspr instruction. Hardware always has full access to
all registers and all register fields in DBSR through the OnCE register access mechanism.
The DBSR register is shown in Figure 511.
Figure 511. DBSR Register
SPR - 304
0123456789101112131415
R
IDE
UDE
MRR
ICMP
BRT
IRPT
TRAP
IAC1
IAC2
IAC3
IAC4
DAC1R
DAC1W
DAC2R
DAC2W
W
Reset
(1)
0001000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RET
0000
DEVT1
DEVT2
00
CIRPT
CRET
VLES
0
DAC_OFST
0
W
Reset0000000000000000
1. Reset by processor reset p_reset_b if DBCR0
EDM
=0, as well as unconditionally by m_por. If DBCR0
EDM
=1, DBERC0
masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by DBERC0
will be reset by p_reset_b. DBSR
MRR
is always updated by p_reset_b however.
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