FlexCAN RM0046
574/936 Doc ID 16912 Rev 5
22.5.1 FlexCAN initialization sequence
The FlexCAN module may be reset in three ways:
â—Ź MCU level hard reset, which resets all memory mapped registers asynchronously
â—Ź MCU level soft reset, which resets some of the memory mapped registers
synchronously (refer to Ta bl e 2 64 to see which registers are affected by soft reset)
â—Ź SOFT_RST bit in MCR, which has the same effect as the MCU level soft reset
Soft reset is synchronous and has to follow an internal request/acknowledge procedure
across clock domains. Therefore, it may take some time to fully propagate its effects. The
SOFT_RST bit remains asserted while soft reset is pending, so software can poll this bit to
know when the reset has completed. Also, soft reset can not be applied while clocks are
shut down in any of the low power modes. The low power mode should be exited and the
clocks resumed before applying soft reset.
The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode.
After the clock source is selected and the module is enabled (MDIS bit negated), FlexCAN
automatically goes to Freeze Mode. In Freeze Mode, FlexCAN is unsynchronized to the
CAN bus, the HALT and FRZ bits in the MCR are set, the internal state machines are
disabled and the FRZ_ACK and NOT_RDY bits in the MCR are set. The Tx pin is in
recessive state and FlexCAN does not initiate any transmission or reception of CAN frames.
Note that the Message Buffers and the Rx Individual Mask Registers are not affected by
reset, so they are not automatically initialized.
For any configuration change/initialization it is required that FlexCAN is put into Freeze
Mode (see Section , “Freeze mode). The following is a generic initialization sequence
applicable to the FlexCAN module:
â—Ź Initialize the Module Configuration Register
– Enable the individual filtering per MB and reception queue features by setting the
BCC bit
– Enable the warning interrupts by setting the WRN_EN bit
– If required, disable frame self reception by setting the SRX_DIS bit
– Enable the FIFO by setting the FEN bit
– Enable the abort mechanism by setting the AEN bit
– Enable the local priority feature by setting the LPRIO_EN bit
â—Ź Initialize the Control Register
– Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
– Determine the bit rate by programming the PRESDIV field
– Determine the internal arbitration mode (LBUF bit)
â—Ź Initialize the Message Buffers
– The Control and Status word of all Message Buffers must be initialized
– If FIFO was enabled, the 8-entry ID table must be initialized
– Other entries in each Message Buffer should be initialized as required
â—Ź Initialize the Rx Individual Mask Registers
â—Ź Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in CTRL
Register (for Bus Off and Error interrupts) and in MCR for Wake-Up interrupt
â—Ź Negate the HALT bit in MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
To Next Page
Loading...
Need help?
General
