ST SPC560P34 - Table 467. Once Status Register Bit Definitions

RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 895/936
Table 467 provides bit definitions for the Once Status Register.
e200z0h OnCE Command Register (OCMD)
The OnCE Command Register (OCMD) is a 10-bit shift register that receives its serial data
from the TDI pin and serves as the instruction register (IR). It holds the 10-bit commands to
be used as input for the e200z0h OnCE Decoder. The Command Register is shown in
Figure 517. The OCMD is updated when the TAP controller enters the Update-IR state. It
contains fields for controlling access to a resource, as well as controlling single-step
operation and exit from OnCE mode.
Although the OCMD is updated during the Update-IR TAP controller state, the
corresponding resource is accessed in the DR scan sequence of the TAP controller, and as
such, the Update-DR state must be transitioned through in order for an access to occur. In
addition, the Update-DR state must also be transitioned through in order for the single-step
Table 467. OnCE Status Register Bit Definitions
Bit(s) Name Description
0MCLK
m_clk Status Bit
0 – Inactive state
1 – Active state
This status bit reflects the logic level on the jd_mclk_on input signal after capture by j_tclk.
1ERR
ERROR
This bit is used to indicate that an error condition occurred during attempted execution of the last
single-stepped instruction (GO+NoExit with CPUSCR or No Register Selected in OCMD), and that
the instruction may not have been properly executed. This could occur if an Interrupt (all classes
including External, Critical, machine check, Storage, Alignment, Program, etc.) occurred while
attempting to perform the instruction single step. In this case, the CPUSCR will contain information
related to the first instruction of the Interrupt handler, and no portion of the handler will have been
executed.
2 CHKSTOP
CHECKSTOP Mode
This bit reflects the logic level on the CPU p_chkstop output after capture by j_tclk.
3 RESET
RESET Mode
This bit reflects the inverted
logic level on the CPU p_reset_b input after capture by j_tclk.
4HALT
HALT Mode
This bit reflects the logic level on the CPU p_halted output after capture by j_tclk.
5STOP
STOP Mode
This bit reflects the logic level on the CPU p_stopped output after capture by j_tclk.
6DEBUG
Debug Mode
This bit is asserted once the CPU is in debug mode. It is negated once the CPU exits debug mode
(even during a debug session)
7WAIT
Waiting Mode
This bit reflects the logic level on the CPU p_waiting output after capture by j_tclk.
8 — Reserved, set to ‘0’ for 1149.1 compliance
9 — Reserved, set to ‘1’ for 1149.1 compliance