RM0046 Error Correction Status Module (ECSM)
Doc ID 16912 Rev 5 291/936
Miscellaneous Interrupt Register (MIR)
All interrupt requests associated with ECSM are collected in the MIR register. This includes
the processor core system bus fault interrupt.
During the appropriate interrupt service routine handling these requests, the interrupt
source contained in the ECSMIR must be explicitly cleared.
Figure 128. Miscellaneous Reset Status Register (MRSR)
Address:
Base + 0x000F Access: User read-only
01234567
RPOR DIR 0000 00
W
Resetxx000000
Table 118. MRSR field descriptions
Field Description
0
POR
Power-On Reset
0 Last recorded event was not caused by a power-on reset (based on a device input signal).
1 Last recorded event was caused by a power-on reset (based on a device input signal).
1
DIR
Device Input Reset
0 Last recorded event was not caused by a device input reset.
1 Last recorded event was a reset caused by a device input reset.
Figure 129. Miscellaneous Interrupt Register (MIR)
Address:
Base + 0x001F Access: User read/write
01234567
RFB0AIFB0SIFB1AIFB1SI0000
W1111xxxx
Reset00000000
Table 119. MIR field descriptions
Field Description
0
FB0AI
Flash Bank 0 Abort Interrupt
0 A flash bank 0 abort has not occurred.
1 A flash bank 0 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing
a 0 has no effect.
1
FB0SI
Flash Bank 0 Stall Interrupt
0 A flash bank 0 stall has not occurred.
1 A flash bank 0 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a
0 has no effect.
2
FB1AI
Flash Bank 1 Abort Interrupt
0 A flash bank 1 abort has not occurred.
1 A flash bank 1 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing
a 0 has no effect.
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