RM0046 Periodic Interrupt Timer (PIT)
Doc ID 16912 Rev 5 787/936
Timer Flag Register n (TFLGn)
These registers contain the PIT interrupt flags.
30.4 Functional description
30.4.1 General
This section gives detailed information on the internal operation of the module. Each timer
can be used to generate trigger pulses as well as to generate interrupts, each interrupt will
be available on a separate interrupt line.
Timers
The timers generate triggers at periodic intervals, when enabled. They load their start
values, as specified in their LDVAL registers, then count down until they reach 0. Then they
load their respective start value again. Each time a timer reaches 0, it will generate a trigger
pulse, and set the interrupt flag.
All interrupts can be enabled or masked (by setting the TIE bits in the TCTRL registers). A
new interrupt can be generated only after the previous one is cleared.
If desired, the current counter value of the timer can be read via the CVAL registers.
The counter period can be restarted, by first disabling, then enabling the timer with the TEN
bit (see Figure 462).
Figure 461. Timer Flag register n (TFLGn)
Address:
Channel Base + 0x000C
TFLG0 = PIT_BASE + 0x010C
TFLG1 = PIT_BASE + 0x011C
TFLG2 = PIT_BASE + 0x012C
TFLG3 = PIT_BASE + 0x013C
Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000 0000000TIF
W
w1c
Reset0000000000000000
Table 422. TFLGn field descriptions
Field Description
TIF
Time Interrupt Flag
TIF is set to 1 at the end of the timer period.This flag can be cleared only by writing it with a 1.
Writing a 0 has no effect. If enabled (TIE = 1), TIF causes an interrupt request.
0: Time-out has not yet occurred
1: Time-out has occurred
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