ST SPC560P34 - Interrupts

RM0046 Periodic Interrupt Timer (PIT)
Doc ID 16912 Rev 5 789/936
30.4.2 Interrupts
All of the timers support interrupt generation. Refer to 9, “Interrupt Controller (INTC) for
related vector addresses and priorities.
Timer interrupts can be disabled by setting the TIE bits to zero. The timer interrupt flags
(TIF) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by
writing a 1 to that TIF bit.
30.5 Initialization and application information
30.5.1 Example configuration
In the example configuration:
● The PIT clock has a frequency of 50 MHz
● Timer 1 creates an interrupt every 5.12 ms
● Timer 3 creates a trigger event every 30 ms
First the PIT module needs to be activated by writing a 0 to the MDIS bit in the PITMCR.
The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to trigger
every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. The
value for the LDVAL register trigger would be calculated as (period / clock period) – 1.
The LDVAL registers must be configured as follows:
● LDVAL for Timer 1: 0x0003_E7FF
● LDVAL for Timer 3: 0x0016_E35F
The interrupt for Timer 1 is enabled by setting TIE in the TCTRL1 register. The timer is
started by writing a 1 to bit TEN in the TCTRL1 register.
Timer 3 shall be used only for triggering. Therefore Timer 3 is started by writing a 1 to bit
TEN in the TCTRL3 register, bit TIE stays at 0.
The following example code matches the described setup:
// turn on PIT
PIT_CTRL = 0x00;
// RTI
PIT_RTI_LDVAL = 0x004C4B3F; // setup RTI for 5000000 cycles
PIT_RTI_TCTRL = PIT_TIE; // let RTI generate interrupts
PIT_RTI_TCTRL |= PIT_TEN; // start RTI
// Timer 1
PIT_LDVAL1 = 0x0003E7FF; // setup timer 1 for 256000 cycles
PIT_TCTRL1 = TIE; // enable Timer 1 interrupts
PIT_TCTRL1 |= TEN; // start timer 1
// Timer 3
PIT_LDVAL3 = 0x0016E35F; // setup timer 3for 1500000 cycles
PIT_TCTRL3 = TEN; // start timer 3