Introduction RM0046
46/936 Doc ID 16912 Rev 5
1 Introduction
1.1 The SPC560P40/34 microcontroller family
The SPC560P40/34 microcontroller is built on the Power Architecture
®
platform. The Power
Architecture
based 32-bit microcontrollers represent the latest achievement in integrated
automotive application controllers. This device family integrates the most advanced and up-
to-date motor control design features.
The safety features included in SPC560P40/34 (such us fault collection unit, safety port or
flash memory and SRAM with ECC) support the design of system applications where safety
is a requirement.
The SPC560P40/34 addresses low-end chassis applications and implements the Harvard
bus interface version of the e200z0h core.
The e200 processor family is a set of CPU cores that implement low-cost versions of the
Power Architecture Book E architecture. The e200 processors are designed for deeply
embedded control applications that require low cost solutions rather than maximum
performance. The e200z0h processor integrates an integer execution unit, branch control
unit, instruction fetch and load/store units, and a multi-ported register file capable to
sustaining three read and two write operations per clock. Most integer instructions execute
in a single clock cycle. Branch target prefetching is performed by branch unit to allow single-
cycle branches in some cases. The e200z0h core is a single-issue, 32-bit Power
Architecture technology VLE only design with 32-bit general purpose registers (GPRs). All
arithmetic instructions that execute in the core operate on data in the general purpose
registers (GPRs). Instead of the base Power Architecture instruction set support, the
e200z0h core only implements the VLE (variable length encoding) APU, providing improved
code density.
The SPC560P40/34 has a single level of memory hierarchy consisting of 20 KB on-chip
SRAM and 320 KB (256 KB program + 64 KB data) of on-chip flash memory. Both the
SRAM and the flash memory can hold instructions and data.
The timer functions of the SPC560P40/34 are performed by the eTimer Modular Timer
System and FlexPWM. The eTimer module implements enhanced timer features (six
channels) including dedicated motor control quadrature decode functionality and DMA
support; the FlexPWM module consists of four submodules controlling a pair of PWM
channels each: three submodules may be used to control the three phases of a motor and
the additional pair to support DC-DC converter width modulation control.
Off-chip communication is performed by a suite of serial protocols including CANs,
enhanced SPIs (DSPI), and SCIs (LINFlex).
The System Integration Unit Lite (SIUL) performs several chip-wide configuration functions.
Pad configuration and general-purpose input/output (GPIO) are controlled from the SIUL.
External interrupts and reset control are also found in the SIUL. The internal multiplexer
sub-block (IOMUX) provides multiplexing of daisy chaining the DSPIs and external interrupt
signal.
As the SPC560P40/34 is built on a wider legacy of Power Architecture-based devices, when
applicable and possible, reuse or enhancement of existing IP, design and concepts is
adopted.
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