Nexus Development Interface (NDI) RM0046
912/936 Doc ID 16912 Rev 5
To single-step the CPU:
● The debugger scans in either a new or a previously saved value of the CPUSCR (with
appropriate modification of the PC and IR as described in Section , “Control State
Register (CTL)), with a Go+Noexit OnCE Command value.
● The debugger scans out the OSR with “no-register selected”, Go cleared, and
determines that the PCU has re-entered the Debug state and that no ERR condition
occurred
To return the CPU to normal operation (without disabling external debug mode)
● The OCR
DMDIS
, OCR
DR
, control bits should be cleared, leaving the OCR
WKUP
bit set
● The debugger restores the CPUSCR with a previously saved value of the CPUSCR
(with appropriate modification of the PC and IR as described in Section , “Control State
Register (CTL)), with a Go+Exit OnCE Command value.
● The OCR
WKUP
bit may then be cleared
To exit External Debug Mode
● The debugger should place the CPU in the debug state via the OCR
DR
with OCR
WKUP
asserted, scanning out and saving the CPUSCR
● The debugger should write the DBCRx registers as needed, likely clearing every
enable except
the DBCR0
EDM
bit
● The debugger should write the DBSR to a cleared state
● The debugger should rewrite the DBCR0 with all bits including EDM cleared
● The debugger should clear the OCR
DR
bit
● The debugger restores the CPUSCR with the previously saved value of the CPUSCR
(with appropriate modification of the PC and IR as described in Section , “Control State
Register (CTL)), with a Go+Exit OnCE Command value.
● The OCR
WKUP
bit may then be cleared
Note: These steps are meant by way of examples, and are not meant to be an exact template for
debugger operation.
36.15 Functional description
The NDI block is implemented by integrating the following blocks on the SPC560P40/34:
● Nexus e200z0 development interface (OnCE subblock)
● Nexus port controller (NPC) block
36.15.1 Enabling Nexus clients for TAP access
After the conditions have been met to bring the NDI out of the reset state, the loading of a
specific instruction in the JTAG controller (JTAGC) block is required to grant the NDI
ownership of the TAP. Each Nexus client has its own JTAGC instruction opcode for
ownership of the TAP, granting that client the means to read/write its registers. The JTAGC
instruction opcode for each Nexus client is shown in Table 4 73. After the JTAGC opcode for
a client has been loaded, the client is enabled by loading its NEXUS-ENABLE instruction.
The NEXUS-ENABLE instruction opcode for each Nexus client is listed in Tabl e 47 4 .
Opcodes for all other instructions supported by Nexus clients can be found in the relevant
sections of this chapter.
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