RM0046 FlexPWM
Doc ID 16912 Rev 5 685/936
The EXT_SYNC signal originates either on- or off-chip, depending on the system
architecture. This signal may be selected as the source for counter initialization so that an
external source can control the period of all submodules.
If the Master Reload signal is selected as the source for counter initialization, then the
period of the counter will be locked to the register reload frequency of submodule 0. Since
the reload frequency is usually commensurate to the sampling frequency of the software
control algorithm, the submodule counter period will therefore equal the sampling period. As
a result, this timer can be used to generate output compares or output triggers over the
entire sampling period, which may consist of several PWM cycles. The Master Reload signal
can only originate from submodule 0.
The counter can optionally initialize upon the assertion of the FORCE_OUT signal
assuming that the FORCE_EN bit is set. As indicated by Figure 371, this constitutes a
second init input into the counter, which causes the counter to initialize regardless of which
signal is selected as the counter init signal. The FORCE_OUT signal is provided mainly for
commutated applications. When PWM signals are commutated on an inverter controlling a
brushless DC motor, it is necessary to restart the PWM cycle at the beginning of the
commutation interval. This action effectively resynchronizes the PWM waveform to the
commutation timing. Otherwise, the average voltage applied to a motor winding integrated
over the entire commutation interval will be a function of the timing between the
asynchronous commutation event with respect to the PWM cycle. The effect is more critical
at higher motor speeds where each commutation interval may consist of only a few PWM
cycles. If the counter is not initialized at the start of each commutation interval, the result will
be an oscillation caused by the beating between the PWM frequency and the commutation
frequency.
25.8.4 PWM generation
Figure 372 illustrates how PWM generation is accomplished in each submodule. In each
case, two comparators and associated VALx registers are utilized for each PWM output
signal. One comparator and VALx register control the turn-on edge, while a second
comparator and VALy register control the turn-off edge.
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