ST SPC560P34 - Figure 386. Full Cycle Reload Frequency Change; Figure 387. Half Cycle Reload Frequency Change; Load Frequency

RM0046 FlexPWM
Doc ID 16912 Rev 5 699/936
LDOK allows software to finish calculating all of these PWM parameters so they can be
synchronously updated. The PSRC, INIT, and VALx registers are loaded by software into a
set of outer buffers. When LDOK is set, these values are transferred to an inner set of
registers at the beginning of the next PWM reload cycle to be used by the PWM generator.
Set LDOK by reading it when it is a logic zero and then writing a logic one to it. After loading,
LDOK is automatically cleared.
25.9.2 Load frequency
The LDFQ bits in the CTRL1 register select an integral loading frequency of one to 16 PWM
reload opportunities. The LDFQ bits take effect at every PWM reload opportunity, regardless
the state of the LDOK bit. The HALF and FULL bits in the CTRL1 register control reload
timing. If FULL is set, a reload opportunity occurs at the end of every PWM cycle when the
count equals VAL1. If HALF is set, a reload opportunity occurs at the half cycle when the
count equals VAL0. If both HALF and FULL are set, a reload opportunity occurs twice per
PWM cycle when the count equals VAL1 and when it equals VAL0.
Figure 386. Full cycle reload frequency change
Figure 387. Half cycle reload frequency change
Counter
Reload
Change
Reload
Frequency
Every
two opportunities
to every
four opportunities
to every
opportunity
Counter
Reload
Change
Reload
Frequency
Every two
opportunities
to every four
opportunities
to every
opportunity