Cross Triggering Unit (CTU) RM0046
614/936 Doc ID 16912 Rev 5
set and (if enabled) an interrupt for an error is performed (in this case at least one register
was written but the update has not ended before the MRS occurrence). If FGRE is 0 it is not
necessary to perform a reload because all the double-buffered registers are unchanged
(see Figure 308).
Figure 308. Reload error scenario
24.6 Power safety mode
To reduce power consumption two mechanisms are implemented:
● MDIS bit in the CTUPCR
● STOP mode
24.6.1 MDIS bit
The MDIS bit in the CTUPCR is used for stopping the clock to all non memory mapped
registers.
24.6.2 STOP mode
To reduce consumption, it is also possible to enable a stop request from the Mode Entry
module. The FIFOs are considered a lot like memory mapped registers, otherwise there
could be some problems if a read operation occurs during the MDIS bit set period. When the
clock is started after an MDIS bit setting or a stop signal, some mistakes could occur. For
example, a wrong trigger could be provided because it was programmed before the stop
signal was performed, and some incorrect write operations into the FIFOs could happen.
For this reason after a stop signal after a MDIS bit setting the FIFO have to be empty. In
order to avoid the problems linked to a wrong trigger, the CTU output can be disabled by the
CTU_ODIS bit
and the ADC interface state machine can be reset by the CRU_ADC_R (see
Section 24.8.21, “Cross triggering unit control register (CTUCR)).
Normal Case
Error Case
MRS
GRE
FGRE
MRS_RE
MRS
GRE
FGRE
MRS_RE
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