ST SPC560P34 - Table 179. EDMA_EEIRL Field Descriptions; Table 180. EDMA_SERQR Field Descriptions; Figure 180. Edma Enable Error Interrupt Low Register (EDMA_EEIRL); Figure 181. Edma Set Enable Request Register (EDMA_SERQR)

RM0046 Enhanced Direct Memory Access (eDMA)
Doc ID 16912 Rev 5 391/936
eDMA Set Enable Request Register (EDMA_SERQR)
The EDMA_SERQR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_ERQRL to enable the DMA request for a given channel. The data value on a register
write causes the corresponding bit in the EDMA_ERQRL to be set. Setting bit 1 (SERQn)
provides a global set function, forcing the entire contents of EDMA_ERQRL to be asserted.
Reads of this register return all zeroes.
Figure 180. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL)
Address: Base + 0x0014 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00
W
Reset0000000000000000
Table 179. EDMA_EEIRL field descriptions
Field Description
16-31
EEIn
Enable error interrupt n.
0 The error signal for channel n does not generate an error interrupt.
1 The assertion of the error signal for channel n generate an error interrupt request.
Figure 181. eDMA Set Enable Request Register (EDMA_SERQR)
Address: Base + 0x0018 Access: User write-only
01234567
R00000000
W
SERQ[0:6]
Reset00000000
Table 180. EDMA_SERQR field descriptions
Field Descriptions
0 Reserved.
1–7
SERQ[0:6]
Set enable request.
0–15 Set corresponding bit in EDMA_ERQRL
16–63Reserved
64–127Set all bits in EDMA_ERQRL
Bit 2 (SERQ1) is not used.