ST SPC560P34 - Figure 404. Comparator Load 1 (CMPLD1); Figure 405. Comparator Load 2 (CMPLD2); Table 378. CMPLD1 Field Descriptions

eTimer RM0046
722/936 Doc ID 16912 Rev 5
Comparator Load register 1 (CMPLD1)
This read/write register is the preload value for the COMP1 register. This register can also
be used to load into the CNTR register. This register is not byte accessible. More
information on the use of this register can be found in Section , “Usage of Compare Load
registers.
Comparator Load register 2 (CMPLD2)
This read/write register is the preload value for the COMP2 register. This register can also
be used to load into the CNTR register. This register is not byte accessible. More
information on the use of this register can be found in Section , “Usage of Compare Load
registers.
TCF2IE
Timer Compare 2 Flag Interrupt Enable
Setting this bit enables interrupts when the TCF2 bit is set.
TCF1IE
Timer Compare 1 Flag Interrupt Enable
Setting this bit enables interrupts when the TCF1 bit is set.
TCFIE
Timer Compare Flag Interrupt Enable
Setting this bit enables interrupts when the TCF bit is set.
Table 377. INTDMA field descriptions (continued)
Field Description
Figure 404. Comparator Load 1 (CMPLD1)
Address:
Base + 0x0018 (eTimer0)
Base + 0x0038 (eTimer1)
Base + 0x0058 (eTimer2)
Base + 0x0078 (eTimer3)
Base + 0x0098 (eTimer4)
Base + 0x00B8 (eTimer5)
Access: User read/write
0123456789101112131415
R
CMPLD1[15:0]
W
Reset0000000000000000
Table 378. CMPLD1 field descriptions
Field Description
CMPLD1[15:0] Specifies the preload value for the COMP1 register.
Figure 405. Comparator Load 2 (CMPLD2)
Address:
Base + 0x001A (eTimer0)
Base + 0x003A (eTimer1)
Base + 0x005A (eTimer2)
Base + 0x007A (eTimer3)
Base + 0x009A (eTimer4)
Base + 0x00BA (eTimer5)
Access: User read/write
0123456789101112131415
R
CMPLD2[15:0]
W
Reset0000000000000000