ST SPC560P34 - Unimplemented Sprs and Read-Only Sprs; Instruction Summary; Figure 120. E200 User Mode Program Model

e200z0 and e200z0h Core RM0046
278/936 Doc ID 16912 Rev 5
Figure 120. e200 User mode program model
12.3.1 Unimplemented SPRs and read-only SPRs
e200 fully decodes the SPR field of the mfspr and mtspr instructions. If the SPR specified
is undefined and not privileged, an illegal instruction exception is generated. If the SPR
specified is undefined and privileged and the CPU is in user mode (MSR[PR=1]), a
privileged instruction exception is generated. If the SPR specified is undefined and
privileged and the core is in supervisor mode (MSR[PR=0]), an illegal instruction exception
is generated.
For the mtspr instruction, if the SPR specified is read-only and not privileged, an illegal
instruction exception is generated. If the SPR specified is read-only and privileged and the
core is in user mode (MSR[PR=1]), a privileged instruction exception is generated. If the
SPR specified is read-only and privileged and the core is in supervisor mode (MSR[PR=0]),
an illegal instruction exception is generated.
12.4 Instruction summary
The e200z0 core supports Power Architecture technology VLE instructions..
USER Mode Programmer Model
SPR 9
General-Purpose
Registers
Count Register
CTR
SPR 8
Link Register
LR
Condition Register
CR
GPR0
GPR1
GPR31
SPR 1
XER
XER
General Registers
Cache Registers
SPR 515
Cache Configuration
(Read-only)
L1CFG0