Internal Static RAM (SRAM) RM0046
310/936 Doc ID 16912 Rev 5
16.5.2 Reset effects on SRAM accesses
Asynchronous reset will possibly corrupt RAM if it asserts during a read or write operation to
SRAM. The completion of that access depends on the cycle at which the reset occurs. If no
access is occurring when reset occurs, RAM corruption does not happen.
Instead synchronous reset (SW reset) should be used in controlled function (without RAM
accesses) in case initialization procedure is needed without RAM initialization.
16.6 Functional description
ECC checks are performed during the read portion of an SRAM ECC read/write (R/W)
operation, and ECC calculations are performed during the write portion of a R/W operation.
Because the ECC bits can contain random data after the device is powered on, the SRAM
must be initialized by executing 32-bit write operations prior any read accesses. This is also
true for implicit read accesses caused by any write accesses smaller than 32 bits as
discussed in Section 16.5, “SRAM ECC mechanism.
16.7 Initialization and application information
To use the SRAM, the ECC must check all bits that require initialization after power on. All
writes must specify an even number of registers performed on 32-bit word-aligned
boundaries. If the write is not the entire 32-bits (8 or 16 bits), a read/modify/write operation
is generated that checks the ECC value upon the read. Refer to Section 16.5, “SRAM ECC
mechanism.
Note: You must initialize SRAM, even if the application does not use ECC reporting.
Write
8 or 16-bit write
Idle
1
Read
Pipelined 8- or 16-bit write
2
32-bit write
8 or 16-bit write
0
(write to the same address)
Pipelined 8, 16 or 32-bit write 8 , 16 or 32-bit write 0
32-bit write
Idle
032-bit write
Read
Table 136. Number of wait states required for SRAM operations (continued)
Operation type Current operation Previous operation Number of wait states required
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