ST SPC560P34 - Figure 210. DSPI Status Register (Dspix_Sr); Table 214. DSPI Baud Rate Scaler; Table 215. Dspix_Sr Field Descriptions

RM0046 Deserial Serial Peripheral Interface (DSPI)
Doc ID 16912 Rev 5 453/936
DSPI Status Register (DSPIx_SR)
The DSPIx_SR contains status and flag bits. The bits are set by the hardware and reflect the
status of the DSPI and indicate the occurrence of events that can generate interrupt or DMA
requests. Software can clear flag bits in the DSPIx_SR by writing a 1 to clear it (w1c).
Writing a 0 to a flag bit has no effect.
Table 214. DSPI baud rate scaler
BR Baud rate scaler value BR Baud rate scaler value
0000 2 1000 256
0001 4 1001 512
0010 6 1010 1024
0011 8 1011 2048
0100 16 1100 4096
0101 32 1101 8192
0110 64 1110 16384
0111 128 1111 32768
Figure 210. DSPI Status Register (DSPIx_SR)
Address: Base + 0x002C Access: User read/write
0123456789101112131415
R TCF TXRXS 0 EOQF TFUF 0 TFFF 0 0000RFOF0RFDF 0
W
w1c w1c w1c w1c w1c w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R TXCTR TXNXTPTR RXCTR POPNXTPTR
W
Reset0000000000000000
Table 215. DSPIx_SR field descriptions
Field Description
0
TCF
Transfer complete flag
Indicates that all bits in a frame have been shifted out. The TCF bit is set after the last incoming
databit is sampled, but before the tASC delay starts. Refer to Section , “Classic SPI transfer format
(CPHA = 0) for details. The TCF bit is cleared by writing 1 to it.
0 Transfer not complete.
1 Transfer complete.
1
TXRXS
TX and RX status
Reflects the status of the DSPI. Refer to Section 20.8.2, “Start and stop of DSPI transfers for
information on what clears and sets this bit.
0 TX and RX operations are disabled (DSPI is in STOPPED state).
1 TX and RX operations are enabled (DSPI is in RUNNING state).