FlexCAN RM0046
564/936 Doc ID 16912 Rev 5
The matching algorithm described above can be changed to be the same one used in
previous versions of the FlexCAN module. When the BCC bit in the MCR is negated, the
matching algorithm stops at the first MB with a matching ID that it founds, whether this MB is
free or not. As a result, the message queueing feature does not work if the BCC bit is
negated.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports
individual masking per MB. Please refer to Section , “Rx Individual Mask Registers
(RXIMR0–RXIMR31). During the matching algorithm, if a mask bit is asserted, then the
corresponding ID bit is compared. If the mask bit is negated, the corresponding ID bit is
“don’t care”. Please note that the Individual Mask Registers are implemented in RAM, so
they are not initialized out of reset. Also, they can only be programmed if the BCC bit is
asserted and while the module is in Freeze Mode.
FlexCAN also supports an alternate masking scheme with only three mask registers
(RGXMASK, RX14MASK and RX15MASK) for backwards compatibility. This alternate
masking scheme is enabled when the BCC bit in the MCR is negated.
Note: The individual Rx Mask per Message Buffer feature may not be available in low cost MCUs.
Please consult the specific MCU documentation to find out if this feature is supported. If not
supported, the RXGMASK, RX14MASK, and RX15MASK registers are available, regardless
of the value of the BCC bit.
22.4.6 Data coherence
In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the
rules described in Transmit process and Section 22.4.4, “Receive process. Any form of CPU
accessing an MB structure within FlexCAN other than those specified may cause FlexCAN
to behave in an unpredictable way.
Transmission abort mechanism
The abort mechanism provides a safe way to request the abortion of a pending
transmission. A feedback mechanism is provided to inform the CPU if the transmission was
aborted or if the frame could not be aborted and was transmitted instead. In order to
maintain backwards compatibility, the abort mechanism must be explicitly enabled by
asserting the AEN bit in the MCR.
In order to abort a transmission, the CPU must write a specific abort code (1001) to the
Code field of the Control and Status word. When the abort mechanism is enabled, the active
MBs configured as transmission must be aborted first and then they may be updated. If the
abort code is written to an MB that is currently being transmitted, or to an MB that was
already loaded into the SMB for transmission, the write operation is blocked and the MB is
not deactivated, but the abort request is captured and kept pending until one of the following
conditions are satisfied:
● The module loses the bus arbitration
● There is an error during the transmission
● The module is put into Freeze Mode
If none of conditions above are reached, the MB is transmitted correctly, the interrupt flag is
set in the IFLAG register and an interrupt to the CPU is generated (if enabled). The abort
request is automatically cleared when the interrupt flag is set. In the other hand, if one of the
above conditions is reached, the frame is not transmitted, therefore the abort code is written
into the Code field, the interrupt flag is set in the IFLAG and an interrupt is (optionally)
generated to the CPU.
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