ST SPC560P34 - Etimer

RM0046 eTimer
Doc ID 16912 Rev 5 703/936
26 eTimer
26.1 Introduction
The eTimer module contains six identical counter/timer channels and one watchdog timer
function. Each 16-bit counter/timer channel contains a prescaler, a counter, a load register,
a hold register, two queued capture registers, two compare registers, two compare preload
registers, and four control registers.
The Load register provides the initialization value to the counter when the counter’s terminal
value has been reached. For true modulo counting the counter can also be initialized by the
CMPLD1 or CMPLD2 registers.
The Hold register captures the counter’s value when other counters are being read. This
feature supports the reading of cascaded counters coherently.
The Capture registers enable an external signal to take a “snapshot” of the counter’s current
value.
The COMP1 and COMP2 registers provide the values to which the counter is compared. If a
match occurs, the OFLAG signal can be set, cleared, or toggled. At match time, an interrupt
is generated if enabled, and the new compare value is loaded into the COMP1 or COMP2
registers from CMPLD1 and CMPLD2 if enabled.
The Prescaler provides different time bases useful for clocking the counter/timer.
The Counter provides the ability to count internal or external events.
Within the eTimer module (set of six timer/counter channels) the input pins are shareable.