RM0046 Flash Memory
Doc ID 16912 Rev 5 313/936
states) for accesses that hit in the holding register. There is no support for prefetching
associated with bank1.
● Programmable response for read-while-write sequences including support for stall-
while-write, optional stall notification interrupt, optional Flash operation termination,
and optional termination notification interrupt
● Separate and independent configurable access timing (on a per bank basis) to support
use across a wide range of platforms and frequencies
● Support of address-based read access timing for emulation of other memory types
● Support for reporting of single- and multi-bit Flash ECC events
● Typical operating configuration loaded into programming model by system reset
17.2.2 Modes of operation
The platform Flash controller module does not support any special modes of operation. Its
operation is driven from the AMBA-AHB memory references it receives from the platform’s
bus masters. Its configuration is defined by the setting of the programming model registers,
physically located as part of the Flash array modules.
17.2.3 External signal descriptions
The platform Flash controller does not directly interface with any external signals. Its primary
internal interfaces include a connection to an AMBA-AHB crossbar (or memory protection
unit) slave port and connections with as many as two banks (code and data) of Flash
memory, each containing one instantiation of the Flash array. Additionally, the operating
configuration for the platform Flash controller is defined by the contents of certain code
Flash array0 registers that are inputs to the module.
17.2.4 Memory map and registers description
Two memory maps are associated with the platform Flash controller: one for the Flash
memory space and another for the program-visible control and configuration registers. The
Flash memory space is accessed via the AMBA-AHB port. The program-visible registers
are accessed via the slave peripheral bus. Details on both memory spaces are provided in
Section , “Memory map.
There are no program-visible registers that physically reside inside the platform Flash
controller. Rather, the platform Flash controller receives control and configuration
information from the Flash array controller(s) to determine the operating configuration.
These are part of the Flash array’s configuration registers mapped into its slave peripheral
(IPS) address space but are described here.
Note: Updating the configuration fields that control the platform flash controller behavior should
only occur while the flash controller is idle. Changing configuration settings while a flash
access is in progress can lead to non-deterministic behavior.
Memory map
First, consider the Flash memory space accessed via transactions from the platform Flash
controller’s AHB port. To support the two separate Flash memory banks, the platform Flash
controller uses address bit 23 (haddr[23]) to steer the access to the appropriate memory
bank. In addition to the actual Flash memory regions, there are shadow and test sectors
included in the system memory map. The program-visible control and configuration registers
associated with each memory array are included in the slave peripheral address region. The
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