ST SPC560P34 - Table 156. PFCR0 Field Descriptions; Figure 160. Platform Flash Configuration Register 0 (PFCR0)

Flash Memory RM0046
354/936 Doc ID 16912 Rev 5
Figure 160. Platform Flash Configuration Register 0 (PFCR0)
Address: Base + 0x001C Access: User read/write
0123456789101112131415
R
BK0_APC BK0_WWSC BK0_RWSC
BK0_RWWC
W
Reset0001100011000111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BK0_RWWC
0000000
BK0_RWWC
B0_P0_BCFG
B0_P0_DPFE
B0_P0_IPFE
B0_P0_PFLM
B0_P0_BFE
W
Reset1000000011101101
Table 156. PFCR0 field descriptions
Field Description
0-4
BK0_APC
Bank0 Address Pipelining Control
This field controls the number of cycles between Flash array access requests. This field must be
set to a value appropriate to the operating frequency of the PFlash. Higher operating frequencies
require non-zero settings for this field for proper Flash operation. This field is set to 0b00010 by
hardware reset.
00000 Accesses may be initiated on consecutive (back-to-back) cycles.
00001 Access requests require one additional hold cycle.
00010 Access requests require two additional hold cycles.
...
11110 Access requests require 30 additional hold cycles.
11111 Access requests require 31 additional hold cycles.
5-9
BK0_WWSC
Bank0 Write Wait State Control
This field controls the number of wait states to be added to the Flash array access time for writes.
This field must be set to a value appropriate to the operating frequency of the PFlash. Higher
operating frequencies require non-zero settings for this field for proper Flash operation. This field
is set to an appropriate value by hardware reset. This field is set to 0b00010 by hardware reset.
00000 No additional wait states are added.
00001 1 additional wait state is added.
00010 2 additional wait states are added.
...
111111 31 additional wait states are added.