RM0046 Flash Memory
Doc ID 16912 Rev 5 353/936
Platform Flash Configuration Register 0 (PFCR0)
The Platform Flash Configuration Register 0 (PFCR0) defines the configuration associated
with Flash memory bank0, which corresponds to the code Flash. The register is described
in Figure 160 and Ta ble 1 56.
Note: This register is not implemented on the data Flash block.
AD[22:3]
9:28
Address 22–3
ADR provides the first failing address in the event of ECC error (MCR[EER] set) or the first failing
address in the event of RWW error (MCR[RWE] set), or the address of a failure that may have
occurred in a FPEC operation (MCR[PEG] cleared). ADR also provides the first address at which a
ECC single error correction occurs (MCR[EDC] set).
The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC
error, and the ECC single error correction. When accessed ADR will provide the address related to
the first event occurred with the highest priority. The priorities between these four possible events
is summarized in Ta ble 1 55.
This address is always a double word address that selects 64 bits.
In case of a simultaneous ECC double error detection on both double words of the same page, bit
AD3 will output 0. The same is valid for a simultaneous ECC single error correction on both double
words of the same page.
In User mode, ADR is read only.
29:31
Reserved
Write these bits has no effect and read these bits always outputs 0.
Table 154. ADR field descriptions (continued)
Field Description
Table 155. ADR content: priority list
Priority level Error flag ADR content
1 MCR[EER] = 1 Address of first ECC Double Error
2 MCR[RWE] = 1 Address of first RWW Error
3 MCR[PEG] = 0 Address of first FPEC Error
4 MCR[EDC] = 1 Address of first ECC Single Error Correction
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