Mode Entry Module (MC_ME) RM0046
182/936 Doc ID 16912 Rev 5
pending bit is not set when the SAFE mode is entered by a software request (i.e.,
programming of ME_MCTL register).
Mode Transition Complete interrupt
Whenever the system fully completes a mode transition (i.e., the S_MTRANS bit of ME_GS
register transits from ‘1’ to ‘0’), the interrupt pending bit I_MTC of the ME_IS register is set,
and an interrupt request is generated if the mask bit M_MTC of the ME_IM register is ‘1’.
The interrupt bit I_MTC is not set when entering low-power modes HALT0 and STOP0 in
order to avoid the same event requesting the immediate exit of these low-power modes.
6.4.6 Peripheral Clock Gating
During all device modes, each peripheral can be associated with a particular clock gating
policy determined by two groups of peripheral configuration registers.
The run peripheral configuration registers ME_RUN_PC0…7 are chosen only during the
software running modes DRUN, TEST, SAFE, and RUN0…3. All configurations are
programmable by software according to the needs of the application. Each configuration
register contains a mode bit which determines whether or not a peripheral clock is to be
gated. Run configuration selection for each peripheral is done by the RUN_CFG bit field of
the ME_PCTL0…143 registers.
The low-power peripheral configuration registers ME_LP_PC0…7 are chosen only during
the low-power modes HALT0 and STOP0. All configurations are programmable by software
according to the needs of the application. Each configuration register contains a mode bit
which determines whether or not a peripheral clock is to be gated. Low-power configuration
selection for each peripheral is done by the LP_CFG bit field of the ME_PCTL0…143
registers.
Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143
registers do not affect the clock gating behavior until a new mode transition request is
generated.
Whenever the processor enters a debug session during any mode, the following occurs for
each peripheral:
● The clock is gated if the DBG_F bit of the associated ME_PCTL0…143 register is set.
Otherwise, the peripheral clock gating status depends on the RUN_CFG and LP_CFG
bits. Any further modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and
ME_PCTL0…143 registers during a debug session will take affect immediately without
requiring any new mode request.
6.4.7 Application Example
Figure 65 shows an example application flow for requesting a mode change and then
waiting until the mode transition has completed.
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