RM0046 Reset Generation Module (MC_RGM)
Doc ID 16912 Rev 5 205/936
The status flag associated with a given ‘destructive’ reset event
(RGM_DES.F_<destructive reset> bit) is set when the ‘destructive’ reset is asserted and the
power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously,
and it is software’s responsibility to determine which reset source is the most critical for the
application.
The device’s low-voltage detector threshold ensures that, when 1.2V low-voltage detected is
enabled, the supply is sufficient to have the destructive event correctly propagated through
the digital logic. Therefore, if a given ‘destructive’ reset is enabled, the MC_RGM ensures
that the associated reset event will be correctly triggered to the full system. However, if the
given ‘destructive’ reset is disabled and the voltage goes below the digital functional
threshold, functionality can no longer be ensured, and the reset may or may not be
asserted.
An enabled destructive reset will trigger a reset sequence starting from the beginning of
PHASE0.
8.4.3 External Reset
The MC_RGM manages the external reset coming from RESET_B. The detection of a
falling edge on RESET_B will start the reset sequence from the beginning of PHASE1.
The status flag associated with the external reset falling edge event (RGM_FES.F_EXR bit)
is set when the external reset is asserted and the power-on reset is not asserted.
The external reset can optionally be disabled by writing bit RGM_FERD.D_EXR.
Note: The RGM_FERD register can be written only once between two power-on reset events.
An enabled external reset will normally trigger a reset sequence starting from the beginning
of PHASE1. Nevertheless, the RGM_FESS register enables the further configuring of the
reset sequence triggered by the external reset. When RGM_FESS.SS_EXR is set, the
external reset will trigger a reset sequence starting directly from the beginning of PHASE3,
skipping PHASE1 and PHASE2. This can be useful especially when an external reset
should not reset the flash.
The MC_RGM may also assert the external reset if the reset sequence was triggered by
one of the following:
● a power-on reset
● a ‘destructive’ reset event
● an external reset event
● a ‘functional’ reset event configured via the RGM_FBRE register to assert the external
reset
In this case, the external reset is asserted until the end of PHASE3.
8.4.4 Functional Resets
A ‘functional’ reset indicates that an event has occurred after which it can be guaranteed
that critical register and memory content is still intact.
The status flag associated with a given ‘functional’ reset event
(RGM_FES.F_<functional reset> bit) is set when the ‘functional’ reset is asserted and the
power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously,
and it is software’s responsibility to determine which reset source is the most critical for the
application.
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