ST SPC560P34 User Manual

RM0046 LIN Controller (LINFlex)
Doc ID 16912 Rev 5 503/936
UART mode status register (UARTSR)
Figure 240. UART mode status register (UARTSR)
Offset: 0x0014 Access: User read/write
0123456789101112131415
R 0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SZF OCF PE3 PE2 PE1 PE0 RMB FEF BOF RPS WUF 0 0 DRF DTF NF
Ww1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c w1c w1c w1c
Reset0000000000000000
Table 242. UARTSR field descriptions
Field Description
SZF
Stuck at Zero Flag
This bit is set by hardware when the bus is dominant for more than a 100-bit time. It is cleared by
software.
OCF
OCF Output Compare Flag
0 No output compare event occurred.
1 The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR.
An interrupt is generated if the OCIE bit in LINIER register is set.
PE3
Parity Error Flag Rx3
This bit indicates if there is a parity error in the corresponding received byte (Rx3). See Section ,
Buffer in UART mode. No interrupt is generated if this error occurs.
0 No parity error.
1 Parity error.
PE2
Parity Error Flag Rx2
This bit indicates if there is a parity error in the corresponding received byte (Rx2). See Section ,
Buffer in UART mode. No interrupt is generated if this error occurs.
0 No parity error.
1 Parity error.
PE1
Parity Error Flag Rx1
This bit indicates if there is a parity error in the corresponding received byte (Rx1). See Section ,
Buffer in UART mode. No interrupt is generated if this error occurs.
0 No parity error.
1 Parity error.
PE0
Parity Error Flag Rx0
This bit indicates if there is a parity error in the corresponding received byte (Rx0). See Section ,
Buffer in UART mode. No interrupt is generated if this error occurs.
0 No parity error.
1 Parity error.

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English