ST SPC560P34 - Figure 275. Rx Individual Mask Registers (RXIMR0-RXIMR31)

FlexCAN RM0046
558/936 Doc ID 16912 Rev 5
Rx Individual Mask Registers (RXIMR0–RXIMR31)
These registers are used as acceptance masks for ID filtering in Rx MBs and the FIFO. If
the FIFO is not enabled, one mask register is provided for each available Message Buffer,
providing ID masking capability on a per Message Buffer basis. When the FIFO is enabled
(FEN bit in MCR is set), the first 8 Mask Registers apply to the 8 elements of the FIFO filter
table (on a one-to-one correspondence), while the rest of the registers apply to the regular
MBs, starting from MB8.
The Individual Rx Mask Registers are implemented in RAM, so they are not affected by
reset and must be explicitly initialized prior to any reception. Furthermore, they can only be
accessed by the CPU while the module is in Freeze Mode. Out of Freeze Mode, write
accesses are blocked and read accesses will return “all zeros”. Furthermore, if the BCC bit
in the MCR is negated, any read or write operation to these registers results in access error.
Note: The individual Rx Mask per Message Buffer feature may not be available in low cost MCUs.
Please consult the specific MCU documentation to find out if this feature is supported. If not
supported, the RXGMASK, RX14MASK and RX15MASK registers are available, regardless
of the value of the BCC bit.
25
BUF6I
Buffer MB6 Interrupt or “FIFO Warning”
If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag
indicates that 4 out of 6 buffers of the FIFO are already occupied (FIFO almost full).
0 No such occurrence.
1 MB6 completed transmission/reception or FIFO almost full.
26
BUF5I
Buffer MB5 Interrupt or “Frames available in FIFO”
If the FIFO is not enabled, this bit flags the interrupt for MB5. If the FIFO is enabled, this flag
indicates that at least one frame is available to be read from the FIFO.
0 No such occurrence.
1 MB5 completed transmission/reception or frames available in the FIFO.
27–31
BUF4I – BUF0I
Buffer MB
i
Interrupt or “reserved”
If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled,
these flags are not used and must be considered as reserved locations.
0 No such occurrence.
1 Corresponding MB completed transmission/reception.
Table 283. IFLAG1 field descriptions (continued)
Field Description
Figure 275. Rx Individual Mask Registers (RXIMR0–RXIMR31)
Address: See Table 285 Access: User read/write
0123456789101112131415
R
MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset0000000000000000