ST SPC560P34 - Figure 329. Control on Time Register (COTR); Table 336. CTUIR Field Descriptions

Cross Triggering Unit (CTU) RM0046
640/936 Doc ID 16912 Rev 5
24.8.20 Control ON time register (COTR)
Table 336. CTUIR field descriptions
Field Description
T7_IE
Trigger 7 Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
T6_IE
Trigger 6 Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
T5_IE
Trigger 5 Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
T4_IE
Trigger 4 Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
T3_IE
Trigger 3 Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
T2_IE
Trigger 2 Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
T1_IE
Trigger 1 Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
T0_IE
Trigger 0 Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
MRS_DMAE
DMA transfer Enable on MRS occurrence if GRE bit is set
0 Interrupt disabled
1 Interrupt enabled
MRS_IE
MRS Interrupt Enable
0 Interrupt disabled
1 Interrupt enabled
IEE
Interrupt Error Enable
0 Interrupt disabled
1 Interrupt enabled
Figure 329. Control ON time register (COTR)
Address: Base + 0x00C6 Access: User read/write
0123456789101112131415
R00000000
COTR
W
Reset0000000000000000