ST SPC560P34 - Table 86. DEBUGPORT Allowed Register Accesses; Table 87. PWCMPH;L Field Descriptions; Figure 94. Password Comparison Register High Word (PWCMPH) Register; Figure 95. Password Comparison Register Low Word (PWCMPL) Register

System Status and Configuration Module (SSCM) RM0046
246/936 Doc ID 16912 Rev 5
Password comparison registers
These registers allow to unsecure the device, if the correct password is known.
Table 86. DEBUGPORT allowed register accesses
Access type
Access width
8-bit 16-bit 32-bit
(1)
Read Allowed Allowed Not allowed
Write Allowed Allowed Not allowed
1. All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC).
Figure 94. Password Comparison Register High Word (PWCMPH) register
Address: Base + 0x000C Access: User read/write
0123456789101112131415
R00000000 00000 000
W PWD_HI[31:16]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000 00000000
W PWD_HI[15:0]
Reset0000000000000000
Figure 95. Password Comparison Register Low Word (PWCMPL) register
Address: Base + 0x0010 Access: User read/write
0123456789101112131415
R00000000 00000 000
W PWD_LO[31:16]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000 00000000
W PWD_LO[15:0]
Reset0000000000000000
Table 87. PWCMPH/L field descriptions
Field Description
PWD_HI[31:0] Upper 32 bits of the password
PWD_LO[31:0] Lower 32 bits of the password