Internal Static RAM (SRAM) RM0046
308/936 Doc ID 16912 Rev 5
16 Internal Static RAM (SRAM)
16.1 Introduction
The general-purpose SRAM has a size of 20 KB.
The SRAM provides the following features:
● SRAM can be read/written from any bus master
● Byte, halfword, word and doubleword addressable
● Single-bit correction and double-bit error detection
16.2 SRAM operating mode
The SRAM has only one operating mode. No standby mode is available.
16.3 Module memory map
The SRAM occupies up to 20 KB of address space.
Table 135 shows the SRAM memory map.
16.4 Register descriptions
The SRAM has no registers. Registers associated with the ECC are located in the ECSM.
See Section , “ECC registers.
16.5 SRAM ECC mechanism
The SRAM ECC detects the following conditions and produces the following results:
● Detects and corrects all 1-bit errors
● Detects and flags all 2-bit errors as non-correctable errors
● Detects 39-bit reads (32-bit data bus plus the 7-bit ECC) that return all zeros or all
ones, asserts an error indicator on the bus cycle, and sets the error flag
SRAM does not detect all errors greater than 2 bits.
Table 134. SRAM operating modes
Mode Configuration
Normal (functional) Allows reads and writes of SRAM
Table 135. SRAM memory map
Address Use
0x4000_0000 (Base) 20 KB RAM
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