RM0046 Flash Memory
Doc ID 16912 Rev 5 323/936
The platform Flash controller inserts additional wait states according to the values of
haddr[28:24],where haddr represents the Flash address. When these inputs are non-zero,
additional cycles are added to AHB read cycles. Write cycles are not affected. In addition,
no page read buffer prefetches are initiated, and buffer hits are ignored.
Table 140 and Table 141 show the relationship of haddr[28:24] to the number of additional
primary wait states. These wait states are applied to the initial access of a burst fetch or to
single-beat read accesses on the AHB system bus.
Note that the wait state specification consists of two components: haddr[28:26] and
haddr[25:24] and effectively extends the Flash read by (8 × haddr[25:24] + haddr[28:26])
cycles.
Table 141 shows the relationship of haddr[25:24] to the number of additional wait states.
These are applied in addition to those specified by haddr[28:26] and thus extend the total
wait state specification capability.
17.2.18 Timing diagrams
Since the platform Flash controller is typically used in platform configurations with a
cacheless core, the operation of the processor accesses to the platform memories, for
example Flash and SRAM, plays a major role in the overall system performance. Given the
core/platform pipeline structure, the platform’s memory controllers (PFlash, PRAM) are
designed to provide a 0 wait state data phase response to maximize processor
Table 140. Additional wait state encoding
Memory address
haddr[28:26]
Additional wait states
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Table 141. Extended additional wait state encoding
Memory address
haddr[25:24]
Additional wait states
(added to those specified by
haddr[28:26])
00 0
01 8
10 16
11 24
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