ST SPC560P34 - Table 124. FEAR Field Descriptions; Table 125. FEMR Field Descriptions; Figure 134. Flash ECC Address Register (FEAR); Figure 135. Flash ECC Master Number Register (FEMR)

RM0046 Error Correction Status Module (ECSM)
Doc ID 16912 Rev 5 299/936
Flash ECC Master Number Register (FEMR)
The FEMR is a 4-bit register for capturing the XBAR bus master number of the last properly
enabled ECC event in the flash memory. Depending on the state of the ECC Configuration
Register, an ECC event in the flash causes the address, attributes and data associated with
the access to be loaded into the FEAR, FEMR, FEAT and FEDR registers, and the
appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is
ignored.
Flash ECC Attributes (FEAT) register
The FEAT is an 8-bit register for capturing the XBAR bus master attributes of the last
properly enabled ECC event in the flash memory. Depending on the state of the ECC
Figure 134. Flash ECC Address register (FEAR)
Address Base + 0x0050 Access: User read-only
0123456789101112131415
R FEAR[31:16]
W
Reset————————————————
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FEAR[15:0]
W
Reset————————————————
Table 124. FEAR field descriptions
Field Description
0-31
FEAR[31:0]
Flash ECC Address Register
This 32-bit register contains the faulting access address of the last properly enabled flash ECC
event.
Figure 135. Flash ECC Master Number Register (FEMR)
Address: Base + 0x0056 Access: User read-only
01234567
R0000 FEMR[3:0]
W
Reset0000––––
Table 125. FEMR field descriptions
Name Description
4-7
FEMR[3:0]
Flash ECC Master Number Register
This 4-bit register contains the XBAR bus master number of the faulting access of the last properly
enabled flash ECC event.