ST SPC560P34 - Figure 469. STM Channel Compare Register (Stm_Cmpn); Table 427. Stm_Cirn Field Descriptions; Table 428. Stm_Cmpn Field Descriptions

System Timer Module (STM) RM0046
794/936 Doc ID 16912 Rev 5
STM Channel Compare Register (STM_CMPn)
The STM Channel Compare Register (STM_CMPn) holds the compare value for channel n.
Table 427. STM_CIRn field descriptions
Field Description
CIF
Channel Interrupt Flag
The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect.
0 No interrupt request.
1 Interrupt request due to a match on the channel.
Figure 469. STM Channel Compare Register (STM_CMPn)
Address:
Base + 0x0018 (STM_CMP0)
Base + 0x0028 (STM_CMP1)
Base + 0x0038 (STM_CMP2)
Access: User read/write
0123456789101112131415
R
CMP
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CMP
W
Reset0000000000000000
Table 428. STM_CMPn field descriptions
Field Description
CMP
Compare value for channel n
If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the STM_CNT register, a
channel interrupt request is generated and the STM_CIRn[CIF] bit is set.