ST SPC560P34 - Interrupts

FlexCAN RM0046
572/936 Doc ID 16912 Rev 5
Once out of Freeze Mode, FlexCAN tries to resynchronize to the CAN bus by waiting for 11
consecutive recessive bits.
Module disable mode
This low power mode is entered when the MDIS bit in the MCR is asserted. If the module is
disabled during Freeze Mode, it shuts down the clocks to the CPI and MBM sub-modules,
sets the LPM_ACK bit and negates the FRZ_ACK bit. If the module is disabled during
transmission or reception, FlexCAN does the following:
● Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission
and then checks it to be recessive
● Waits for all internal activities like arbitration, matching, move-in and move-out to finish
● Ignores its Rx input pin and drives its Tx pin as recessive
● Shuts down the clocks to the CPI and MBM sub-modules
● Sets the NOT_RDY and LPM_ACK bits in MCR
The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped
registers, except the Free Running Timer, the Error Counter Register, and the Message
Buffers, which cannot be accessed when the module is in Disable Mode. Exiting from this
mode is done by negating the MDIS bit, which will resume the clocks and negate the
LPM_ACK bit.
Stop mode
This is a system low power mode in which all MCU clocks are stopped for maximum power
savings. If FlexCAN receives the global Stop Mode request during Freeze Mode, it sets the
LPM_ACK bit, negates the FRZ_ACK bit and then sends a Stop Acknowledge signal to the
CPU, in order to shut down the clocks globally. If Stop Mode is requested during
transmission or reception, FlexCAN does the following:
● Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission
and checks it to be recessive
● Waits for all internal activities like arbitration, matching, move-in and move-out to finish
● Ignores its Rx input pin and drives its Tx pin as recessive
● Sets the NOT_RDY and LPM_ACK bits in MCR
● Sends a Stop Acknowledge signal to the CPU, so that it can shut down the clocks
globally
Stop Mode is exited by the CPU resuming the clocks and removing the Stop Mode request.
22.4.10 Interrupts
The module can generate as many as 38 interrupt sources (32 interrupts due to message
buffers and 6 interrupts due to ORed interrupts from MBs, Bus Off, Error, Tx Warning, Rx
Warning, and Wake Up). The number of actual sources depends on the configured number
of Message Buffers.
Each one of the message buffers can be an interrupt source if its corresponding IMASK bit
is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under the
assumption that the buffer is initialized for either transmission or reception. Each of the
buffers has assigned a flag bit in the IFLAG Registers. The bit is set when the corresponding
buffer completes a successful transmission/reception and is cleared when the CPU writes it
to 1 (unless another interrupt is generated at the same time).