ST SPC560P34 - Delay Settings; Table 231. Delay Values

Deserial Serial Peripheral Interface (DSPI) RM0046
482/936 Doc ID 16912 Rev 5
20.9.3 Delay settings
Table 231 shows the values for the delay after transfer (t
DT
) and CS to SCK delay (t
CSC
) that
can be generated based on the prescaler values and the scaler values set in the
DSPIx_CTARs. The values calculated assume a 100 MHz system frequency.
20.9.4 Calculation of FIFO pointer addresses
The user has complete visibility of the TX and RX FIFO contents through the FIFO registers,
and valid entries can be identified through a memory mapped pointer and a memory
mapped counter for each FIFO. The pointer to the first-in entry in each FIFO is memory
mapped. For the TX FIFO the first-in pointer is the transmit next pointer (TXNXTPTR). For
the RX FIFO the first-in pointer is the pop next pointer (POPNXTPTR).
Refer to Section , “Transmit First In First Out (TX FIFO) buffering mechanism and Section ,
“Receive First In First Out (RX FIFO) buffering mechanism for details on the FIFO operation.
The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
Table 231. Delay values
Delay prescaler values
(DSPI_CTAR[PBR])
1357
Delay scaler values (DSPI_CTAR[DT])
2 20.0 ns 60.0 ns 100.0 ns 140.0 ns
4 40.0 ns 120.0 ns 200.0 ns 280.0 ns
8 80.0 ns 240.0 ns 400.0 ns 560.0 ns
16 160.0 ns 480.0 ns 800.0 ns 1.1 s
32 320.0 ns 960.0 ns 1.6 s2.2 s
64 640.0 ns 1.9 s3.2 s4.5 s
128 1.3 s3.8 s6.4 s9.0 s
256 2.6 s7.7 s 12.8 s17.9 s
512 5.1 s 15.4 s 25.6 s35.8 s
1024 10.2 s 30.7 s 51.2 s71.7 s
2048 20.5 s 61.4 s 102.4 s 143.4 s
4096 41.0 s 122.9 s 204.8 s 286.7 s
8192 81.9 s 245.8 s 409.6 s 573.4 s
16384 163.8 s 491.5 s 819.2 
s 1.1 ms
32768 327.7 s 983.0 s 1.6 ms 2.3 ms
65536 655.4 s 2.0 ms 3.3 ms 4.6 ms