ST SPC560P34 - Critical Interrupt Taken Debug Event

RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 867/936
an Interrupt Taken debug event. This event can occur and be recorded in DBSR regardless
of the setting of MSR
DE
. When an Interrupt Taken debug event occurs, the DBSR
IRPT
bit is
set to ‘1’ to record the debug exception. The value saved in DSRR0 will be the address of
the non-critical interrupt handler.
36.10.8 Critical Interrupt Taken Debug Event
A Critical Interrupt Taken debug event (CIRPT) occurs if Critical Interrupt Taken debug
events are enabled (DBCR0
CIRPT
=1) and a critical interrupt (other than a Debug interrupt
when the Debug APU is disabled) occurs. Only critical class interrupts cause a Critical
Interrupt Taken debug event. This event can occur and be recorded in DBSR regardless of
the setting of MSR
DE
. When a Critical Interrupt Taken debug event occurs, the DBSR
CIRPT
bit is set to ‘1’ to record the debug exception. The value saved in DSRR0 will be the address
of the critical interrupt handler. Note that this debug event should not normally be enabled
unless the Debug APU is also enabled to avoid corruption of CSRR0/1.
36.10.9 Return Debug Event
A Return debug event (RET) occurs if Return debug events are enabled (DBCR0
RET
=1) and
an attempt is made to execute an se_rfi instruction. This event can occur and be recorded
in DBSR regardless of the setting of MSR
DE
. When a Return debug event occurs, the
DBSR
RET
bit is set to ‘1’ to record the debug exception.
If MSR
DE
=0 and DBCR0
EDM
=0 at the time of the execution of the se_rfi (i.e. before the
MSR is updated by the se_rfi), then DBSR
IDE
is also set to ‘1’ to record the imprecise debug
event.
If MSR
DE
=1 at the time of the execution of the se_rfi, a Debug interrupt will occur provided
there exists no higher priority exception which is enabled to cause an interrupt. Debug
Save/Restore Register 0 will be set to the address of the se_rfi instruction.
36.10.10 Critical Return Debug Event
A Critical Return debug event (CRET) occurs if Critical Return debug events are enabled
(DBCR0
CRET
=1) and an attempt is made to execute an se_rfci instruction. This event can
occur and be recorded in DBSR regardless of the setting of MSR
DE
. When a Critical Return
debug event occurs, the DBSR
CRET
bit is set to ‘1’ to record the debug exception.
If MSR
DE
=0 and DBCR0
EDM
=0 at the time of the execution of the se_rfci (i.e. before the
MSR is updated by the se_rfci), then DBSR
IDE
is also set to ‘1’ to record the imprecise
debug event.
If MSR
DE
=1 at the time of the execution of the se_rfci, a Debug interrupt will occur provided
there exists no higher priority exception which is enabled to cause an interrupt. Debug
Save/Restore Register 0 will be set to the address of the se_rfci instruction. Note that this
debug event should not normally be enabled unless the Debug APU is also enabled to avoid
corruption of CSRR0/1.
36.10.11 External Debug Event
An External debug event (DEVT1, DEVT2) occurs if External debug events are enabled
(DBCR0
DEVT1
=1 or DBCR0
DEVT2
=1), and the respective p_devt1 or p_devt2 input signal
transitions to the asserted state. This event can occur and be recorded in DBSR regardless
of the setting of MSR
DE
. When an External debug event occurs, DBSR
DEVT{1,2}
is set to ‘1’
to record the debug exception.