Error Correction Status Module (ECSM) RM0046
288/936 Doc ID 16912 Rev 5
15.4.2 Registers description
Attempted accesses to reserved addresses result in an error termination, while attempted
writes to read-only registers are ignored and do not terminate with an error. Unless noted
otherwise, writes to the programming model must match the size of the register, e.g., an n-
bit register only supports n-bit writes, etc. Attempted writes of a different size than the
register width produce an error termination of the bus cycle and no change to the targeted
register.
Processor core type (PCT) register
The PCT is a 16-bit read-only register that specifies the architecture of the processor core in
the device. The state of this register is defined by a module input signal; it can only be read
from the IPS programming model. Any attempted write is ignored.
Revision (REV) register
The REV is a 16-bit read-only register specifying a revision number. The state of this
register is defined by an input signal; it can only be read from the IPS programming model.
Any attempted write is ignored.
0x006C REDR—RAM ECC Data register on page 15-305 32
0x0070–0x3FFF Reserved
Table 112. ECSM registers (continued)
Offset from
ECSM_BASE
0xFFF4_0000
Register Location Size (bits)
Figure 123. Processor core type (PCT) register
Address:
Base + 0x0000 Access: User read-only
0123456789101112131415
R PCT[15:0]
W
Reset1110000000010010
Table 113. PCT field descriptions
Name Description
0-15
PCT[15:0]
Processor Core Type
0xE012 identifies the z0H Power Architecture.
Figure 124. Revision (REV) register
Address:
Base + 0x0002 Access: User read-only
0123456789101112131415
R REV[15:0]
W
Reset0000000000000000
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