ST SPC560P34 - Error Correction Status Module (ECSM); Introduction; Overview; Features

Error Correction Status Module (ECSM) RM0046
286/936 Doc ID 16912 Rev 5
15 Error Correction Status Module (ECSM)
15.1 Introduction
The Error Correction Status Module (ECSM) provides control functions for the device
Standard Product Platform (SPP) including program-visible information about the platform
configuration and revision levels, a reset status register, a software watchdog timer, and
wakeup control for exiting sleep modes, and optional features such as an address map for
the device’s crossbar switch, information on memory errors reported by error-correcting
codes and/or generic access error information for certain processor cores. It also provides
with register access protection for the following slave modules: INTC, ECSM, STM, and
SWT.
15.2 Overview
The Error Correction Status Module is mapped into the IPS space and supports a number of
control functions for the platform device.
15.3 Features
The ECSM includes these features:
● Program-visible information on the platform device configuration and revision
● Reset status register (MRSR)
● Registers for capturing information on platform memory errors if error-correcting codes
(ECC) are implemented
● Registers to specify the generation of single- and double-bit memory data inversions for
test purposes if error-correcting codes are implemented
● Access address information for faulted memory accesses for certain processor core
micro-architectures
● XBAR priority functions, including forcing round robin and high priority enabling
● Capability to restrict register access to supervisor mode to selected on-platform slave
devices: INTC, ECSM, STM, and SWT
15.4 Memory map and registers description
This section details the programming model for the ECSM. This is an on-platform 128-byte
space mapped to the region serviced by an IPS bus controller. Some of the control registers
have a 64-bit width. These 64-bit registers are implemented as two 32-bit registers, and
include an “H” and “L” suffixes, indicating the “high” and “low” portions of the control function.
The Error Correction Status Module does not include any logic that provides access control.
Rather, this function is supported using the standard access control logic provided by the
IPS controller.
ECSM registers are accessible only when the core is in supervisor mode (see
Section 15.4.3, “ECSM_reg_protection).