RM0046 Deserial Serial Peripheral Interface (DSPI)
Doc ID 16912 Rev 5 439/936
The DSPI supports these SPI features:
● Full-duplex, three-wire synchronous transfers
● Master and slave modes
● Buffered transmit and receive operation using the TX and RX FIFOs, with depths of 5
entries
● Visibility into TX and RX FIFOs for ease of debugging
● FIFO bypass mode for low-latency updates to SPI queues
● Programmable transfer attributes on a per-frame basis
– 8 clock and transfer attribute registers
– Serial clock with programmable polarity and phase
– Programmable delays
CS to SCK delay
SCK to CS delay
Delay between frames
– Programmable serial frame size of 4 to 16 bits, expandable with software control
– Continuously held chip select capability
● 8 peripheral chip selects, expandable to 64 with external demultiplexer
● Deglitching support for as many as 32 peripheral chip selects with external
demultiplexer
● 2 DMA conditions for SPI queues residing in RAM or flash
– TX FIFO is not full (TFFF)
– RX FIFO is not empty (RFDF)
● 6 interrupt conditions:
– End of queue reached (EOQF)
– TX FIFO is not full (TFFF)
– Transfer of current frame complete (TCF)
– RX FIFO is not empty (RFDF)
– FIFO overrun (attempt to transmit with an empty TX FIFO or serial frame received
while RX FIFO is full) (RFOF)
– FIFO under flow (slave only and SPI mode, the slave is asked to transfer data
when the TX FIFO is empty) (TFUF)
● Modified SPI transfer formats for communication with slower peripheral devices
● Continuous serial communications clock (SCK)
● Maximum baud rate:
– Classic SPI Transfer Format—8 Mbit/s
– Modified SPI Transfer Format—16 Mbit/s
20.5 Modes of operation
The DSPI has four modes of operation. These modes can be divided into two categories;
module-specific modes such as master, slave, and module disable modes, and a second
category that is an MCU-specific mode: debug mode. All four modes are implemented on
this device.
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