RM0046 DMA Channel Mux (DMA_MUX)
Doc ID 16912 Rev 5 427/936
19.3.2 Register descriptions
Channel Configuration Registers
Each of the DMA channels can be independently enabled/disabled and associated with one
of the #SRC + #ALE total DMA sources in the system.
Note: Setting multiple CHCONFIG registers with the same Source value will result in
unpredictable behavior.
Note: Before changing the trigger or source settings a DMA channel must be disabled via the
CHCONFIG[#n].ENBL bit.
Figure 200. Channel Configuration Registers (CHCONFIG#n)
Address: Base + #n Access: User read/write
76543210
R
ENBL TRIG SOURCE
W
Reset00000000
Table 201. CHCONFIG#x field descriptions
Field Description
7
ENBL
DMA Channel Enable
ENBL enables the DMA Channel.
0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The
DMA has separate channel enables/disables that should be used to disable or reconfigure a DMA
channel.
1 DMA channel is enabled.
6
TRIG
DMA Channel Trigger Enable (for triggered channels only)
TRIG enables the periodic trigger capability for the DMA Channel.
0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel routes the
specified source to the DMA channel.
1 Triggering is enabled.
5–0
SOURCE
DMA Channel Source (slot)
SOURCE specifies which DMA source, if any, is routed to a particular DMA channel. See Table 203.
Table 202. Channel and trigger enabling
ENBL TRIG Function Mode
0 X DMA Channel is disabled Disabled Mode
1 0 DMA Channel is enabled with no triggering (transparent) Normal Mode
1 1 DMA Channel is enabled with triggering
Periodic Trigger
Mode
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