DMA Channel Mux (DMA_MUX) RM0046
426/936 Doc ID 16912 Rev 5
All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses
must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit
boundaries. As an example, CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit
READ/WRITE to address ‘Base + 0x0000’, but performing a 32-bit access to address ‘Base
+ 0x0001’ is illegal.
0x0005 Channel #5 Configuration (CHCONFIG5) on page 19-427
0x0006 Channel #6 Configuration (CHCONFIG6) on page 19-427
0x0007 Channel #7 Configuration (CHCONFIG7) on page 19-427
0x0008 Channel #8 Configuration (CHCONFIG8) on page 19-427
0x0009 Channel #9 Configuration (CHCONFIG9) on page 19-427
0x000A Channel #10 Configuration (CHCONFIG10) on page 19-427
0x000B Channel #11 Configuration (CHCONFIG11) on page 19-427
0x000C Channel #12 Configuration (CHCONFIG12) on page 19-427
0x000D Channel #13 Configuration (CHCONFIG13) on page 19-427
0x000E Channel #14 Configuration (CHCONFIG14) on page 19-427
0x000F Channel #15 Configuration (CHCONFIG15) on page 19-427
0x0010 Channel #16 Configuration (CHCONFIG16) on page 19-427
0x0011 Channel #17 Configuration (CHCONFIG17) on page 19-427
0x0012 Channel #18 Configuration (CHCONFIG18) on page 19-427
0x0013 Channel #19 Configuration (CHCONFIG19) on page 19-427
0x0014 Channel #20 Configuration (CHCONFIG20) on page 19-427
0x0015 Channel #21 Configuration (CHCONFIG21) on page 19-427
0x0016 Channel #22 Configuration (CHCONFIG22) on page 19-427
0x0017 Channel #23 Configuration (CHCONFIG23) on page 19-427
0x0018 Channel #24 Configuration (CHCONFIG24) on page 19-427
0x0019 Channel #25 Configuration (CHCONFIG25) on page 19-427
0x001A Channel #26 Configuration (CHCONFIG26) on page 19-427
0x001B Channel #27 Configuration (CHCONFIG27) on page 19-427
0x001C Channel #28 Configuration (CHCONFIG28) on page 19-427
0x001D Channel #29 Configuration (CHCONFIG29) on page 19-427
0x001E Channel #30 Configuration (CHCONFIG30) on page 19-427
0x001F–0x3FFF Reserved
Table 200. DMA_MUX memory map (continued)
Offset from
DMA_MUX_BASE
(0xFFFD_C000)
Register Location
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