Mode Entry Module (MC_ME) RM0046
156/936 Doc ID 16912 Rev 5
Table 45. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions
Field Description
PREVIOUS_MODE
Previous device mode — These bits show the mode in which the device was prior to the
latest change to the current mode.
0000 RESET
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT0
1001 reserved
1010 STOP0
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
MPH_BUSY
MC_ME/MC_PCU Handshake Busy indicator — This bit is set if the MC_ME has requested a
mode change from the MC_PCU and the MC_PCU has not yet responded. It is cleared when
the MC_PCU has responded.
0 Handshake is not busy
1 Handshake is busy
PMC_PROG
MC_PCU Mode Change in Progress indicator — This bit is set if the MC_PCU is in the
process of powering up or down power domains. It is cleared when all power-up/down
processes have completed.
0 Power-up/down transition is not in progress
1 Power-up/down transition is in progress
CORE_DBG
Processor is in Debug mode indicator — This bit is set while the processor is in debug mode.
0 The processor is not in debug mode
1 The processor is in debug mode
SMR
SAFE mode request from MC_RGM is active indicator — This bit is set if a hardware SAFE
mode request has been triggered. It is cleared when the hardware SAFE mode request has
been cleared.
0 A SAFE mode request is not active
1 A SAFE mode request is active
VREG_CSRC_SC
Main VREG dependent Clock Source State Change during mode transition indicator — This
bit is set when a clock source which depends on the main voltage regulator to be powered-up
is requested to change its power up/down state. It is cleared when the clock source has
completed its state change.
0 No state change is taking place
1 A state change is taking place
CSRC_CSRC_SC
(Other) Clock Source dependent Clock Source State Change during mode transition indicator
— This bit is set when a clock source which depends on another clock source to be powered-
up is requested to change its power up/down state. It is cleared when the clock source has
completed its state change.
0 No state change is taking place
1 A state change is taking place
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