eTimer RM0046
732/936 Doc ID 16912 Rev 5
Whenever any counter is read within a counter module, all of the counters’ values within the
module are captured in their respective HOLD registers. This action supports the reading of
a cascaded counter chain. First read any counter of a cascaded counter chain, then read
the HOLD registers of the other counters in the chain. The cascaded counter mode is
synchronous.
Note: It is possible to connect counters together by using the other (non-cascade) counter modes
and selecting the outputs of other counters as a clock source. In this case, the counters are
operating in a “ripple” mode, where higher order counters will transition a clock later than a
purely synchronous design.
One channel can be cascaded with any other channel, but channels cannot be cascaded
more than two deep. Separate cascades of pairs of channels can be created. For example,
channels 0 and 1 can be cascaded, and channels 5 and 4 cascaded separately. However,
channels 0, 1, and 5 cannot be cascaded.
PULSE-OUTPUT mode
When the counter is set up with CNTMODE = 001, and the OFLAG OUTMODE is set to
1111 (gated clock output), and the ONCE bit is set, then the counter will output a pulse
stream of pulses that has the same frequency of the selected clock source, and the number
of output pulses is equal to the compare value minus the init value. This mode is useful for
driving step motor systems.
Note: This does not work if the PRISRC is set to 11000.
Figure 416. Pulse Output mode
FIXED-FREQUENCY PWM mode
When the counter is set up for CNTMODE = 001, count through roll-over (LENGTH = 0),
continuous count (ONCE = 0) and the OFLAG OUTMODE is 0111 (set on compare, cleared
on counter roll-over) then the counter output yields a Pulse Width Modulated (PWM) signal
with a frequency equal to the count clock frequency divided by 65,536 and a pulse width
duty cycle equal to the compare value divided by 65,536. This mode of operation is often
used to drive PWM amplifiers used to power motors and inverters.
VARIABLE-FREQUENCY PWM mode
When the counter is setup for CNTMODE = 001, count till compare (LENGTH = 1),
continuous count (ONCE = 0) and the OFLAG OUTMODE is 0100 (toggle OFLAG and
alternate compare registers) then the counter output yields a Pulse Width Modulated (PWM)
signal whose frequency and pulse width is determined by the values programmed into the
COMP1 and COMP2 registers, and the input clock frequency. This method of PWM
Pulse Stream Init
0 1
0 1 2 3 4 0
LOAD = 0, COMP1 = 4
CNTMODE
Primary
CNTR
OFLAG
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