ST SPC560P34 - Alternate Module Clock Domains; Flexcan Clock Domains; SWT Clock Domains; Cross Triggering Unit (CTU) Clock Domains

Clock Description RM0046
96/936 Doc ID 16912 Rev 5
4.3 Alternate module clock domains
This section lists the different clock domains for each module. If not otherwise noted, all
modules on the SPC560P40/34 device are clocked on the SYS_CLK.
4.3.1 FlexCAN clock domains
The FlexCAN modules have two distinct software controlled clock domains. One of the clock
domains is always derived from the system clock. This clock domain includes the message
buffer logic. The source for the second clock domain can be either the system clock
(SYS_CLK) or a direct feed from the oscillator pin XOSC_CLK. The logic in the second
clock domain controls the CAN interface pins. The CLK_SRC bit in the FlexCAN CTRL
register selects between the system clock and the oscillator clock as the clock source for the
second domain. Selecting the oscillator as the clock source ensures very low jitter on the
CAN bus. System software can gate both clocks by writing to the MDIS bit in the FlexCAN
MCR. Figure 262 shows the two clock domains in the FlexCAN modules.
Refer to 22, “FlexCAN for more information on the FlexCAN modules.
4.3.2 SWT clock domains
The SWT module has two distinct clock domains. The first clock domain (Module Clock) is
always supplied from the SYS_CLK. This clock domain includes the register interface.
The source for the second clock domain (Protocol Clock) is always the IRC generated by the
internal RC oscillator.
4.3.3 Cross Triggering Unit (CTU) clock domains
The CTU module has two distinct clock domains. The first clock domain (Module Clock) is
supplied from the SYS_CLK. This clock domain includes the Command Buffer logic.
The source for the second clock domain (Protocol Clock) is the MC_PLL_CLK. The logic in
the Protocol Clock domain controls the CTU interface pins to the eTimer module and the
ADC module.
4.3.4 Peripherals behind the IPS bus clock sync bridge
FlexPWM clock domain
The FlexPWM module has only one clock domain. The FlexPWM module is clocked from
the MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.
eTimer_0 clock domain
The eTimer_0 module has only one clock domain. The eTimer_0 module is clocked from the
MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.
ADC_0 clock domain
The ADC_0 module has only one clock domain. The ADC_0 module is clocked from the
MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.