Flash Memory RM0046
320/936 Doc ID 16912 Rev 5
Buffer allocation
Allocation of the line read buffers is controlled via page buffer configuration (Bx_Py_BCFG)
field. This field defines the operating organization of the four page buffers. The buffers can
be organized as a “pool” of available resources (with all four buffers in the pool) or with a
fixed partition between buffers allocated to instruction or data accesses. For the fixed
partition, two configurations are supported. In one configuration, buffers 0 and 1 are
allocated for instruction fetches and buffers 2 and 3 for data accesses. In the second
configuration, buffers 0, 1, and 2 are allocated for instruction fetches and buffer 3 reserved
for data accesses.
Buffer invalidation
The page read buffers may be invalidated under hardware or software control.
Any falling edge transition of the array’s bkn_fl_done signal causes the page read buffers to
be marked as invalid. This input is negated by the Flash array at the beginning of all
program/erase operations as well as in certain other cases. Buffer invalidation occurs at the
next AHB non-sequential access boundary, but does not affect a burst from a page read
buffer in progress.
Software may invalidate the buffers by clearing the Bx_Py_BFE bit, which also disables the
buffers. Software may then re-assert the Bx_Py_BFE bit to its previous state, and the buffers
will have been invalidated.
One special case needing software invalidation relates to page buffer “hits” on Flash data
that was tagged with a single-bit ECC event on the original array access. Recall that the
page buffer structure includes an status bit signaling the array access detected and
corrected a single-bit ECC error. On all subsequent buffer hits to this type of page data, a
single-bit ECC event is signaled by the platform Flash controller. Depending on the specific
hardware configuration, this reporting of a single-bit ECC event may generate an ECC alert
interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be
invalidated by software after the first notification of the single-bit ECC event.
Finally, the buffers are invalidated by hardware on any non-sequential access with a non-
zero value on haddr[28:24] to support wait state emulation.
17.2.15 Bank1 temporary holding register
Recall the bank1 logic within the Flash includes a single 128-bit data register, used for
capturing read data. Since this bank does not support prefetching, the read data for the
referenced address is bypassed directly back to the AHB data bus. The page is also loaded
into the temporary data register and subsequent accesses to this page can hit from this
register, if it is enabled (B1_Py_BFE).
The organization of the temporary holding register is described as follows, in a pseudo-code
representation. The hardware structure includes the buffer address and valid bit, along with
128 bits of page read data and several error flags and is the same as an individual bank0
page buffer.
struct { // bk1_page_buffer
reg addr[23:4];// page address
reg valid; // valid bit
reg rdata[127:0];// page read data
reg xfr_error; // transfer error indicator from Flash array
reg multi_ecc_error;// multi-bit ECC error indicator from Flash array
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