RM0046 FlexCAN
Doc ID 16912 Rev 5 543/936
Figure 265. Module Configuration Register (MCR)
Address:
Base + 0x0000 Access: User read/write
0123456789101112131415
R
MDIS FRZ FEN HALT
NOT_
RDY
WAK
_MSK
SOFT
_RST
FRZ_
ACK
SUPV
0
WRN
_EN
LPM_
ACK
00
SRX
_DIS
BCC
W
Reset
1
101100
0
100
1
0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0
LPRI
O_EN
AEN
00
IDAM
00
MAXMB
W
Reset0000000000001111
Table 273. MCR field descriptions
Field Description
0
MDIS
Module Disable
This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the
clocks to the CAN Protocol Interface and Message Buffer Management submodules. This is the
only bit in MCR not affected by soft reset. See Section , “Module disable mode for more
information.
0 Enable the FlexCAN module.
1 Disable the FlexCAN module.
1
FRZ
Freeze Enable
The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR is set or when Debug
Mode is requested at MCU level. When FRZ is asserted, FlexCAN is able to enter Freeze Mode.
Negation of this bit field causes FlexCAN to exit from Freeze Mode.
0 Not able to enter Freeze Mode.
1 Able to enter Freeze Mode.
2
FEN
FIFO Enable
This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot
be used for normal reception and transmission because the corresponding memory region (0x80–
0xFF) is used by the FIFO engine. See Section 22.3.3, “Rx FIFO structure and Section 22.4.7, “Rx
FIFO for more information.
0 FIFO disabled.
1 FIFO enabled.
3
HALT
Halt FlexCAN
Assertion of this bit puts the FlexCAN module into Freeze Mode. The CPU should clear it after
initializing the Message Buffers and Control Register. No reception or transmission is performed by
FlexCAN before this bit is cleared. While in Freeze Mode, the CPU has write access to the Error
Counter Register, that is otherwise read-only. Freeze Mode can not be entered while FlexCAN is in
any of the low power modes. See Section , “Freeze mode for more information.
0 No Freeze Mode request.
1 Enters Freeze Mode if the FRZ bit is asserted.
4
NOT_RDY
FlexCAN Not Ready
This read-only bit indicates that FlexCAN is either in Disable Mode, Stop Mode or Freeze Mode. It
is negated once FlexCAN has exited these modes.
0 FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode.
1 FlexCAN module is either in Disable Mode, Stop Mode or Freeze Mode.
To Next Page
Loading...
Need help?
General
